Characterization of multilevel interconnect capacitance for 0.35µm CMOS technology / Faizul Othman

This thesis presents a methodology for an interconnect capacitance characterization for 0.35µm CMOS technology with three-level metals. The purpose of this work is to generate a capacitance table for the new MIMOS 0.35µm CMOS process and compare with the previous back end process. The generated table is based on simulation results from Raphael field solver simulation tools. Parasitic capacitance database is created and capacitance rules file are generated for parasitic extraction using layout parameter extraction (LPE) tools, Calibre xRC. The methodology starts with plate capacitor measurement, followed by field solver simulation, and finally data verification. This methodology proves sufficiently accurate enough in technology library characterization for MIMOS 0.35µm CMOS process. The comparison of the process shows that the interconnect capacitance from the new process increased due to the smaller design rules implemented.