Low power CMOS charge sharing dynamic latch comparator using 0.18μm technology: article / Nurul Aisyah Nadiah Zainal Abidin

High speed and low power are important in designing a comparator. This thesis discusses the design and analysis of a latching comparator using charge sharing circuit topology for produce low power and high speed. The charge sharing topology combines the good features of the resistive dividing comparator and the differential current sensing comparator. The comparator design is focusing on the minimization of propagation delay and the power dissipation of the comparator, which will improves the comparator performance. This thesis will discuss how this project experimenting the length, width, supply voltage, and load capacitance to obtain the low power and high speed comparator. The simulation results have been obtained using 0.18μm technology, for a 100 MHz clocked comparator, considering 1.8V supply voltage and 1.8V input range. The simulation results are derived using SILVACO EDA tool, the schematic simulation are using Gateway SILVACO EDA tool and layout simulation of design are verified using Expert SILVACO EDA tool. The results show that the proposed technology produces better performance over previous work with 1.827ns propagation delay, 23.18nW power dissipation and average power of 2.56mW.