A low power 0.18µm CMOS technology integrating dual-slope analog-to digital converter

In this thesis work, a 4-bit integrating dual slope analog-to digital converter (DSADC) is designed which consumes low power and simplicity but slow conversion time utilizing a Silvaco Electronic Design Automation (SEDA) tools with an advanced 0.18µm CMOS Technology using 1.8V power supply. Various and different types of ADC are provided in the literature review to assist the writer and reader in depth understanding of the ADC’s system and function. Dual Slope ADC has its own name and famous for high accuracy, high resolution, inexpensive, good noise rejection and ideal for digitizing low bandwidth signal. The proposed DS- ADC contains three main components of integrator, comparator and control logic at which the integrator is realized with a two-stage operational amplifier (op-amp). An Nchannel input two-stage op-amp was chosen in this project for its ICMR is near to the supply voltage and provides sufficient gain. Simulation confirms that the proposed ADC architecture consumes no external DAC module and shows a power efficiency of 2.47392mW at a conversion time of 1.06µs.