Silvaco modelling and characterization of bulk and partially depleted devices for 0.35 and 0.5 µm channel gate length / Syed Omar Farouq Syed Mashor

This thesis presents about the Silvaco Modelling and Characterization of BulkSi and Partially Depleted SOI (PD SOI) Devices for 0.35 and 0.5 µm Channel Gate Length. Two scales of channel lengths, 0.35µm and 0.5µm have been used for the comparison. The comparisons are focused on three main electrical characteristics which are leakage current, threshold voltage and subthreshold voltage for bulk-Si nMOSFET and PD SOI technology. The structure of n-MOSFET is constructed using Silvaco Athena and its electrical characteristics are examined by Silvaco Atlas. From the result analysis shown that the electrical characteristics of Partially-Depleted SOI devices reduce threshold voltage, subthreshold slope and leakage currents as compared to bulk-Si devices [1]. Lowering the threshold voltage means that the supply voltage can be reduced significantly without degrading device speed performance and reduce time taken for device to turn on or turn off [2]. Next, steeper subthreshold slope is desirable due to low power application for the device [3]. Moreover, lower leakage will give advantage since it is suitable for high speed application [3]. Hence, the comparisons that have made shown that 0.5µm channel gate length produced better electrical characteristics compared to 0.35µm channel gate length. However, all the issues and weakness in electrical characteristics as the device shrinks can be improved using SOI technology. Finally, a summary of the work is presented along with insights gained toward future research as the device scaling down.