Comparative study on dynamic latch comparators using 90nm technology: article / Muhammad Hafiz Sahrin

This paper shared three different upgraded CMOS dynamic latch comparator topologies used for pipeline analog to digital converters; there are resistive divider, differential pair and charge sharing latch comparators. All three designs are compared focused in aspect of minimization of propagation delay and the power dissipation, currently needed to improves comparator performance. Furthermore measuring on average power dissipation and voltage offset. Test structures of the comparators, fabricated in 90nm CMOS process carried out by Gateway SILAVACO EDA tool, considering 1.2V supply and be measured to determine the properties differences of the compared topologies. Preliminary simulation shows that the charge sharing latch is the smallest in minimization of power dissipation of 2nW.