Characterization of latchup behavior in CMOS technology / Norisyam Naseri

Naseri, Norisyam (2004) Characterization of latchup behavior in CMOS technology / Norisyam Naseri. Degree thesis, Universiti Teknologi MARA (UiTM).

Abstract

Latch-up behaviour of 0.35 um CMOS Technology is characterized based on current voltage measurement set up. Comparison is also done between 0.35 um and 1um technology. Measurement is done at wafer level on MIMOS 0.35um test structure The two knee points of the switching point (Vs, Is) and holding point (Vh, Ih) are demonstrated and measured from the IV plot. Simulation of a latchup model using Circuit Maker 2000 is also carried out to suggest effects of substrate resistance to the behavior of latch-up. The curve found is similar to theory and the experimental data

Metadata

Item Type:	Thesis (Degree)
Creators:	Creators Email / ID Num. Naseri, Norisyam UNSPECIFIED
Contributors:	Contribution Name Email / ID Num. Thesis advisor Wan Abdullah, Wan Fazlida Hanim UNSPECIFIED
Subjects:	T Technology > TK Electrical engineering. Electronics. Nuclear engineering T Technology > TK Electrical engineering. Electronics. Nuclear engineering > Microelectronics
Divisions:	Universiti Teknologi MARA, Shah Alam > Faculty of Electrical Engineering
Programme:	Bachelor of Electrical Engineering (Hons.)
Keywords:	CMOS technology, MIMOS 0.35um, latchup model using Circuit Maker 2000.
Date:	8 March 2004
URI:	https://ir.uitm.edu.my/id/eprint/114956