Simulations of the strained S10.3GEO.7/S1 for NMOS

The aim of this paper is to design the strained Si₀̣̣₃Ge₀̣₇ on relaxed Si N-MOS semiconductor and to compare the electrical characteristics with the conventional Si NMOS using a device simulator SILVACO. In the first part, the simulation of basic fabrication processes to create the material of conventional Si NMOS devices will be developed. In the second part, the material of the Si₀̣₃Ge₀̣₇ N-MOS will be developed and interfaced with Si. In this part, simulation of the electrical characteristics will be done and compared with the process in the first part. From the electrical characteristics, the results will prove that the Si₀̣₃Ge₀̣₇ N-MOS gives better performance compared to the conventional Si N-MOS. Based on the simulated electrical characteristics; the strained SiGe/Si heterostructure influences the threshold voltage, Vt. The faster turn on of transistor is important to achieve a high speed in complementary MOS technology. The process and device simulation method have proved that the SiGe NMOS is much better performance than Si NMOS in term of low Vt and higher Id saturation as shown in I-V curves. A lower Vt means less power supplies and faster to turn on. Different thickness also contributes to the I-V characteristic. The impurity that used in the device also effects the I-V characteristic.