Optimization of initialization module of DNA sequence alignment accelerator: article / Zaharuddin Maksud

This paper presents the development and implementation of the initialization module of the DNA sequence alignment accelerator. The scopes of this paper focus on the memory r eduction and speed optimization on tbe initialization module using parallelism and divide and conquer methodologies. The development of the optimization using data compression technique is presented in this paper. In this paper, the development target is Xilinx Spartan 3E FPGA using 50 MHz oscillator clock. The code is written in Verilog HDL usin2 Xilinx ISE 10.1 and simulation testbench developed using Xilin.x ISE 10.1 simulation tool Theoritical analysis and simulation results have been compared in this paper.