Low power sample and hold circuit for pipelined ADC using 0.18µm CMOS technology / Nurhakimah Abd Aziz

This paper discusses the design and analysis of the improved sample-and-hold circuit as a front-end block of low power and high gain pipelined analog to digital converter (ADC). This research will use switch-capacitor sample and hold circuit (SHC) which is exploiting multistage amplifier to minimize power consumption. In this study, the switch-capacitor SHC is compared with previous sample-and-hold circuit which the folded-cascode amplifier was used. Simulation results have been obtained using 0.18μm technology, for a 5MHz sampling frequency, considering 1.2 Vpp voltage and 1.8V voltage supply. From the simulation, the SHC consumes 0.139mW. The circuit simulate using SILVACO EDA tool, the schematic simulation are using Gateway SILVACO EDA tool and layout simulation of design are verified using Expert SILVACO EDA tool.