Comparative study on 90nm CMOS SRAM sense amplifiers / Noh Hud Basemu

This paper will investigate the sensing delay optimization and power consumption of each sense amplifier. The optimization will apply multi-Vth or MTCMOS techniques for better sensing delay, with the critical path transistors will use low-Vth model. The initial optimization is done by calculating for the most proper transistor sizing in term of sensing delay and power. The result obtained shows MTCMOS design improves sensing delay in term of smaller bit-lines difference (BL) required for full-swing amplification as compared to single std-Vth. MTCMOS design also improves total power consumption at least 12% reduction as compared to single std-Vth design. The selected sense amplifier circuits to be simulated are Current Sense Amplifier (CSA), Charge-Transfer Sense Amplifier (CTSA), and High-Speed Sense Amplifier (HSSA). The SRAM used is basic 6T SRAM for general purpose only.