8-bit successive approximation register analog-to-digital (SAR ADC) logic design: article / Zuhaila Abdul Halim

Abdul Halim, Zuhaila (2006) 8-bit successive approximation register analog-to-digital (SAR ADC) logic design: article / Zuhaila Abdul Halim. pp. 1-6.

Abstract

A 8-bit SAR logic of SAR ADC has been realized in a HP 0.5μm SCN3M Complementary Metal Oxide Semiconductor (CMOS) process. The power consumption is 3.59mW with resolution of 8-bit. The speed is 125KHz with the supply voltage of 5V. The SAR logic has been designed in custom design approach.

Item Details

Item Type:	Article
Creators:	Creators Email / ID Num. Abdul Halim, Zuhaila UNSPECIFIED
Subjects:	T Technology > TK Electrical engineering. Electronics. Nuclear engineering > Electronics > Applications of electronics
Divisions:	Universiti Teknologi MARA, Shah Alam > Faculty of Electrical Engineering
Page Range:	pp. 1-6
Keywords:	Successive approximation register (SAR) Analog to digital converter (ADC), SAR logic, power consumption, CMOS, resolution
Date:	2006
URI:	https://ir.uitm.edu.my/id/eprint/113343

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