Fabrication and characterization of 130nm PMOS device using Silvaco simulator / Nur Hidayah Othman

Nowadays, downsizing the size of metal-oxide semiconductor field effect transistor (mosfet) is the recent trends in MOSFET technologies such as the aggressive scaling of gate length, the decrease in on-current with scaling, and the increased demand for a variety of transistor types for use in a wide range of target products. This research is focused on the development of 0.13um channel length of pchannel (pmos) enhancement mode MOSFET. Simulation of the process is carried out using silvaco athena to modify theoretical values and obtain accurate process parameters. The most common effect that occurs in the short channel MOSFETS are channel modulation, drain induced barrier lowering (dibl), punch-through and hot electron effect. Several advanced method such as lightly-doped drain (ldd), halo implant and retrograde well is applied to reduce the short channel effects. At the device simulation process, the electrical parameter is extracted to investigate the device characteristics. Several design analysis are performed to investigate the effectiveness of the advanced method in order to prevent the varying of threshold voltage or short channel effect of a mosfet device.