Flood Monitoring Warning System using FPGA / Ahmad Al-Zubir Zulkifly

The paper describes the design and development of Flood Monitoring Warning System (FMWS) using FPGA. This system is based on the measurement of water level and flow rate in real time. The water level and flow rate sensors are used to indicate any chances on the water level or velocity especially during heavy rain. By monitoring the water level and flow rate of any rivers, it can buy sufficient time for resident to evacuate nearby areas, preventing loss of life and property. This system offers complete, low cost, low power consumption, ease of installation, and user friendly way of 24-hours real time monitoring of FMWS when compared with available systems which are either more costly or unreliable. The heart of the design is described using Verilog HDL (Hardware Description Language) and implemented in hardware using Field Programmable Gate Array (FPGA). This design is prototyped on Altera`s Cyclone DE2 FPGA board.