Modelling and simulation of baseband processor for UHF RFID reader on FPGA / Ismarani Ismail and A. Ibrahim

Ismail, Ismarani and Ibrahim, A. (2013) Modelling and simulation of baseband processor for UHF RFID reader on FPGA / Ismarani Ismail and A. Ibrahim. Journal of Electrical and Electronic Systems Research (JEESR), 6: 6. pp. 56-70. ISSN 1985-5389

Abstract

A baseband processor of UHF RFID reader that presented in this paper is based on International Organization for Standardization and International Electrotechnical Commission (ISO/IEC 18000-6) protocol. The protocol also known Electronic Product Code (EPC) Class-1 Generation-2 Radio Frequency Identification (RFID) protocol. The baseband processor consists of PIE encoder, FM0 decoder and Miller decoder. The behavior of the PIE encoder, FM0 decoder and Miller decoder architecture is realized by derivation of Verilog Hardware Description Language (HDL) code in Quartus II software. Utilizing the ModelSimAltera, the encoder and decoder architecture is simulated to observe its functionality. The designing of the encoder and decoder is intended for uses in
Ultra High Frequency (UHF) RFID passive interrogator.

Metadata

Item Type: Article
Creators:
Creators
Email / ID Num.
Ismail, Ismarani
UNSPECIFIED
Ibrahim, A.
azlina.uitm@gmail.com
Subjects: T Technology > TK Electrical engineering. Electronics. Nuclear engineering > Radio frequency identification systems
Divisions: Universiti Teknologi MARA, Shah Alam > Faculty of Electrical Engineering
Journal or Publication Title: Journal of Electrical and Electronic Systems Research (JEESR)
UiTM Journal Collections: UiTM Journal > Journal of Electrical and Electronic Systems Research (JEESR)
ISSN: 1985-5389
Volume: 6
Page Range: pp. 56-70
Keywords: RFID, UHF Reader, FPGA, Baseband Processor
Date: June 2013
URI: https://ir.uitm.edu.my/id/eprint/62952
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