Intelligence Sejadah using VHDL and FPGA / Wan Mohd Nazmin Bin Wan Mahmud

Wan Mahmud, Wan Mohd Nazmin (2008) Intelligence Sejadah using VHDL and FPGA / Wan Mohd Nazmin Bin Wan Mahmud. [Student Project] (Unpublished)


This project is to develop a hardware that includes of designing, synthesizing and evaluation skills based on Field-Programmable Gate Array (FPGA) by using Project Navigator Xilinx ISE’s Software as a workspace for VHDL and ModelSim Simulation Software as a platform to simulate and analysis the design environment with Timing Diagram. Spartan-3 Kit Board will be used as hardware interface and directly connected to the Model of Intelligence Sejadah by using I/O ports. The design rule is based on counter controller described in ASM Chart and then is translated into VHDL descriptions. This project aims to design an Intelligence Sejadah that can count the number of rakaat was and will perform by the user during Solat. The Intelligence Sejadah helps to keep the worshipper alert with rakaat and comfortable during the prostrations of prayer. Intelligence Sejadah will count the rakaat based on Touch-Switch Circuit and displaying the number of rakaat on Seven-Segment LED Display as indicator for user controlled by FPGA user I/O pins.


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