Integration and synthesize of Triple DES using Synopsys Design Compiler targeting for ASIC implementation

This paper presents a project that integrates and synthesize the Verilog Hardware Description Language (HDL) of the Triple Data Encryption System (DES) using Synopsys Design Compiler targeting for ASIC implementation using TSMC 0.25µm technology library. The target is to check on timing analysis whether it met the time constraints or not, and to find out the critical path that leads to the delay of the circuit, then a gate level netlist is generated as to proceed to the next step of the design flow which is the placement and routing, for further ASIC implementation.